The invention relates generally to image sensing circuits arrays, and more particularly to the method and apparatus for testing the arrays.
A conventional sensing array is composed of individual light sensitive circuits called pixels that are organized in rows and columns. A row of pixels has a common line connecting the control gates of their respective access transistors. Data is passed from a pixel through its access transistor to a data line. Each column of pixels is connected to a common data line. During the manufacture of a sensor array, open or short circuits may occur between adjacent row lines or adjacent data lines due to the presence of dust or other particulate matter. Open or short circuiting of row lines or data lines may also occur due to improper control of the etching process.
CMOS image sensor arrays can employ several types of pixels. Passive pixel sensor circuits are comprised of a simple photodiode and an access transistor. Active pixel sensor (APS) circuits have added features including a reset transistor and a source follower amplifier. Individual sensor circuits may suffer from similar problems as the row lines and data lines, in that they may be either short circuited or open circuited and therefore do not perform their proper function. In order to overcome these problems, defects in the sensor array must be detected in order to select arrays that are acceptable for use.
Integrated image sensors have traditionally been relatively expensive devices, many of which used a technology known as charge coupled device (CCD). The nature of these devices did not permit the use of extensive integrated test features, therefore testing was primarily dependent on the use of external light sources. This traditional test method continued for the testing of CMOS image sensors such as those using APS circuits. Therefore, testing of integrated imager active pixel sensor arrays has required the use of expensive, calibrated light sources to perform optical testing of the sensors. Typically, during production testing, an image sensor would be exposed to light of varying intensity ranging from black to white. Measurements would be taken to determine the response of the array. The length of time required to perform these optical tests can be excessive, adding dramatically to the cost of the device. Reduction of test times and therefore costs can be accomplished by reducing the dependency of these tests on a calibrated light source.
In addition to the time required to test an integrated imager array using a calibrated light source, the accuracy of the test is also a concern. If two neighboring pixels were shorted together during the manufacturing process, the measured output would be the same as if the pixels were not shorted together. This occurs because both pixels have been exposed to the same intensity of light. The defect may go undetected until the device is placed in a system and tested under xe2x80x9creal worldxe2x80x9d conditions. Unfortunately, detection of the defect is dependent on human viewing of the output as displayed on the viewing device (e.g. a cathode ray tube or liquid crystal display panel). As the number of pixels on an integrated circuit expands, it becomes increasingly difficult for a human to detect such faults. Special training is required for the human observers and even then, human interpretation plays a major role in the determination of acceptable products. However, humans lack consistent observational skills due to their very nature and varying levels of alertness throughout the day. Therefore, this type of testing is not acceptable for high volume, cost sensitive sensor products.
Other testing methods have been proposed. U.S. Pat. No. 5,276,400 which issued to Denyer et al on Jan. 4, 1994 discloses a test arrangement which does not require the irradiation of the array by a light source. Test circuitry is integrated at the periphery of the sensor array which attempts to drive digital test patterns on the row access lines and data lines. The resulting signal patterns can then be compared to expected values to determine the presence of production faults. This is a much faster test method than those mentioned previously. However, the arrangement proposed by Denyer et al has two major shortcomings. It is suited for passive pixel arrays but not for arrays of active pixel sensors. In an active pixel array, it would only allow for the testing of row line and data line integrity and not for the testing of the individual pixel structures. In addition, digital test patterns are used and these will not necessarily provide accurate results since during actual operation, the voltages obtained on the data lines are analog signals due to the nature of the sensor array.
Another test system is disclosed by U.S. Pat. No. 5,451,768 which issued to Hosier et al on Sep. 19, 1995. This system involves test circuitry integrated on the same die as the sensor array for testing a specific pixel and transfer circuit arrangement. This arrangement involves a circuit for injecting a certain amount of charge into the transfer circuit and a smaller amount of charge to bias the photodiode. The difference between these two charges is indicative of the linear response of the pixel. The test circuit places a known amount of bias charge into the pixel. The pixel is not illuminated during testing, so this bias charge should be shifted out through the transfer circuit. This allows testing for the presence of the correct bias charge and for the proper photodiode response linearity. However, this system does not account for the identification of problems with the row lines or data lines such as short circuits between adjacent lines or open circuits in an individual line.
U.S. Pat. No.5,654,537 which issued to Prater on Aug. 5, 1997 also proposes a system for testing an image scanner array having pixel sensor circuits arranged in rows and columns. Prater""s apparatus includes a reset voltage source having selectable voltage that may vary in amplitude between ground and the supply voltage levels. The photo-sensitive devices in the pixel sensor circuits are cyclically tested using a different selected voltage for each cycle to reset the photosensitive devices in the pixel sensor circuits. During each cycle, the outputs of the pixel sensor circuits are sensed to determine whether they are functioning properly. By varying the reset voltage between ground and the power supply as disclosed by Prater, the pixel sensor circuits are tested as if they had received different illumination levels without the need for a calibrated light source. However, the system does not differentiate between adjacent pixel sensor circuits. Prater discloses supplying the variable reset voltage to the drain of the reset transistors in the pixel sensor circuits in the rows and columns. If two neighbouring pixels were shorted together, the measured output would be the same as if the pixels were not faulty because both pixels would have been reset to the same voltage.
Therefore, there is a need for a method and apparatus capable of testing individual radiation sensitive circuits in an image sensing array as well as the supply and control lines in the array.
The invention is directed to a method and apparatus for testing an image sensor array having sensor circuits arranged in rows and columns. The method includes resetting the voltage of the photosensitive device in each of the sensor circuits such that adjacent circuits are reset to different voltage levels, and then sensing the voltage on each of the reset photosensitive devices.
In accordance with one aspect of the invention, the voltage resetting step includes applying common reset voltages to sensor circuits in the columns such that adjacent columns receive different reset voltage amplitudes and applying common enable voltage signals to the sensor circuits in the rows such that adjacent rows receive different enable signal amplitudes.
In accordance with another aspect of this invention, the voltage sensing step includes sensing the columns of sensor circuits in parallel and the rows of sensor circuits sequentially.
In accordance with a further aspect of this invention, the sensed voltage from the photosensitive devices is compared to expected values to determine faulty sensor circuits or faulty components in the sensor array.
In accordance with another aspect, the present invention is particularly applicable to an image sensor array having sensor circuits arranged in rows and columns and wherein each sensor circuit includes a photosensitive device, a first switch for applying a reset voltage from a voltage reset line to the photosensitive device under the control of a reset signal, a second switch for sensing the voltage on the photosensitive device under the control of an enable signal and applying it to a data line.
The apparatus for testing an image sensor array having sensing circuits arranged in rows and columns wherein the sensing circuits include photosensitive devices comprises a supply circuit for resetting the voltage of the photosensitive device in each of the sensor circuits such that at least adjacent circuits are reset to different voltage levels and a detector for sensing the voltage on each of the photosensitive devices. The apparatus may further include a circuit for comparing the sensed voltages from the photosensitive devices to expected voltage levels to identify faulty components or sensor circuits in the sensor array.
In accordance with another aspect of this invention, the apparatus may include a first set of conductive lines for providing different reset voltages to adjacent columns of sensing circuits, a second set of conductive lines for providing different voltage reset enable signals to adjacent rows of sensing circuits, a third set of conductive lines for providing access signals to rows of sensing circuits for detecting the reset voltages on the sensing circuits, and a fourth set of lines connected to columns of sensing circuits to receive the detected reset voltages. In addition, the comparator circuit may be connected to the fourth set of lines and compares the detected reset voltages to expected voltage levels to identify faulty components in the sensor array. The apparatus may further include a circuit coupled to each of the second set of conductive lines for generating the voltage reset enable signals, and a first voltage supply may be coupled to each of the voltage reset enable signal generating circuits for supplying different voltages to adjacent enable signal generating circuits.
In accordance with a specific aspect of this invention, a second voltage supply provides a first voltage level V1 to alternate lines in the first set of conductive lines and a second voltage level V2 to the remaining lines in the first set of conductive lines whereas the first voltage supply provides a third voltage level V3 to alternate voltage reset signal generating circuits and a fourth voltage level V4 to the remaining voltage reset signal generating circuits. In addition, V1 may be equal to V3 and V2 may be equal to V4.
These differing voltages may be provided to the testing apparatus from an external source through bond pads on the array die. Alternatively, one or more of the voltages could be generated by a circuit integrated on the same die as the image sensor array.
In accordance with a further aspect of the invention, the comparison circuit may be integrated on the array chip to allow the sensor circuit output values to be compared to the expected values without being sent off chip. This has the advantage of reducing the required complexity of the system used to test the imaging IC.
Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of the invention in conjunction with the accompanying drawings.